package queue_operations is
	type operation is (enqueue, dequeue, no_op);
end package queue_operations;

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
use work.queue_operations.all;

-- Test bench for the Priority Queue	
entity test_bench is
end entity test_bench;

architecture test_fifo of test_bench is
	signal clk, reset, empty, full : std_logic;
	signal data_in : std_logic_vector(31 downto 0) := "00000000000000000000000000000001";
	signal data_out : std_logic_vector(31 downto 0);   
	signal priority_in : std_logic_vector(3 downto 0) := "0001";
	signal operation_in : operation;
begin
	dut: entity work.priority_queue(behav)
		port map(data_in, priority_in, operation_in, clk, reset, empty, full, data_out);
		
	
	--enqueue process test bench
	enqueue_process : process is 
	begin
		
		priority_in <= "0001";wait for 10ns;
		data_in <= "00000000000000000000000000000001"; wait for 10ns;
		operation_in <= enqueue; wait for 10ns;
		operation_in <= no_op; wait for 10ns; 
		
		priority_in <= "0100";wait for 10ns;
		data_in <= "00000000000000000000000000000010"; wait for 10ns;
		operation_in <= enqueue; wait for 10ns;
		operation_in <= no_op; wait for 10ns;
		
		priority_in <= "0011";wait for 10ns;
		data_in <= "00000000000000000000000000000101"; wait for 10ns;
		operation_in <= enqueue; wait for 10ns;
		operation_in <= no_op; wait for 10ns; 
		
		priority_in <= "0010";wait for 10ns;
		data_in <= "00000000000000000000000000000011"; wait for 10ns;
		operation_in <= enqueue; wait for 10ns;
		operation_in <= no_op; wait for 10ns; 
		
		--operation_in <= dequeue; wait for 10ns;
		--operation_in <= no_op; wait for 10ns;

	end process enqueue_process;		
	
	--clock process test bench
	clock : process is
	begin
		clk <= '0'; wait for 5ns;
		clk <= '1'; wait for 5ns;
	end process clock;	 
	
	--clock process test bench
	reset_proc : process is
	begin
		reset <= '0'; wait for 200ns;
		--reset <= '1'; wait for 10ns;
		--reset <= '0'; wait for 200ns;
	end process reset_proc;
end architecture test_fifo;